All students must validate 30 ECTS per semester.We offer two speciality tracks:

Track 1: Vision and Applications
The first track focuses on various applications of computer vision: biomedical applications, people detection, object tracking, computational photography.

Track 2: Vision and devices
The second track focuses on devices to capture images (intelligent sensors, medical imaging systems) and to visualise and interact with them (augmented reality)




Course name: High-level Synthesis Methods on FPGA-s Credits: 5

  • Class type: lecture/lab
  • Hours per week: 2/2
  • Type of the exam: oral exam
  • Prerequisites (if exist): FPGA-based Algorithm Design


Summary of the course:

Digital circuits are traditionally designed using specialized hardware description languages like VHDL and Verilog in the Register Transfer Level (RTL). The increasing complexity of today digital systems requires more efficient and flexible design methodologies. High Level Synthesis (HLS) methods are an active research area since 1980s and finally matured to use in industrial applications. Unlike traditional VHDL based design flows the input of a HLS synthesis system is a standard ANSI C/C++ description and the structure of the synthesized architecture can be defined using compiler directives. By changing the directives less design effort and much shorter time is required to generate several different architectures for the same algorithm. Area, speed, power dissipation, memory bandwidth parameters of the different solutions can be compared during design space exploration and the best one can be selected for a particular implementation.

The aim of the course is to give an insight to modern HLS design methodologies and systems. Students will gain experience in designing, simulating, and optimizing of algorithms and creating digital circuits using HLS system.

  1. Introduction to HLS flow, binding, allocation, scheduling, control path generation
  2. Overview of field programmable system-on-chip (SoC) architectures, the Xilinx Zynq architecture
  3. Modeling arbitrary width data types in C/C++
  4. The ARM AMBA AXI-4 bus system
  5. Simulation, on-chip verification
  6. Interface synthesis, interface types, control signals
  7. Synthesis of arrays, array transformations, handling dependencies
  8. Synthesis of loops I: Pipelining
  9. Synthesis of loops II: Unrolling
  10. Synthesis of functions, hierarchical designs
  11. AXI DMA infrastructure IP cores
  12. Hardware / Software partitioning
  13. Case study I: Image processing system
  14. Case study II: Smith-Waterman algorithm

Case study III: Solving partial differential equations

Required reading

Michael Fingeroff, “High-Level Synthesis Blue Book”, Xlibris, 2010

Philippe Coussy, Adam Morawiec, “High-Level Synthesis: from Algorithm to Digital Circuit”, Springer, 2008

Louise Crockett, Ross Elliot, Martin Enderwitz, Bob Stewart, David Northcote, “The Zynq Book Tutorials for Zybo and ZedBoard”, Strathclyde Academic Media, 2015

Xilinx Vivado Design Suite User Guide: High-Level Synthesis

Xilinx Vivado Design Suite Tutorial: High-Level Synthesis

Recommended reading

Raul Camposano and Wayne Wolf, eds., “High-Level VLSI Synthesis”, Springer, 1991.

Sumit Gupta, Rajesh Gupta, Nikil D. Dutt, Alexandru Nicolau, “SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits”, Springer, 2004.

  • Lecturer (name, position, degree): Dr. Zoltán Nagy, associate professor, PhD
  • Additional lecturers, if exist(name, position, degree): Dr. András Kiss, senior lecturer, PhD

The European Credit Transfer and Accumulation System (ECTS) is a student-centred system based on the student workload required to achieve the objectives of a programme of study. Its aim is to facilitate the recognition of study periods undertaken abroad by mobile students through the transfer credits. The ECTS is based on the principle that 60 credits are equivalent to the workload of full-time student during one academic year.