High-level Synthesis Methods on FPGA-s

First semester: PPKE, Budapest
Dr. Zoltán NAGY, PhD, associate professor


Digital circuits are traditionally designed using specialized hardware description languages like VHDL and Verilog in the Register Transfer Level (RTL). The increasing complexity of today digital systems requires more efficient and flexible design methodologies. High Level Synthesis (HLS) methods are an active research area since 1980s and finally matured to use in industrial applications. Unlike traditional VHDL based design flows the input of a HLS synthesis system is a standard ANSI C/C++ description and the structure of the synthesized architecture can be defined using compiler directives. By changing the directives less design effort and much shorter time is required to generate several different architectures for the same algorithm. Area, speed, power dissipation, memory bandwidth parameters of the different solutions can be compared during design space exploration and the best one can be selected for a particular implementation.

For more information, please download the teaching guide HERE.

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